Magnetic Pulse Compression Design for Plasma Ignition Modules

Magnetic Pulse Compression Design for Plasma Ignition Modules

Abstract

Thick and coated plate needs an ignition pulse that combines high voltage, high current and a fast edge, and a semiconductor switch alone handles that duty badly. This article gives the saturable-core equations, the compression ratio arithmetic, a three-stage chain worked through in numbers, four design pain points, six implementation steps and the instrumentation that shows the chain working.

1. Einleitung

Striking an arc on thick, coated or highly conductive plate needs an ignition pulse with high peak voltage, high peak current and a fast edge at the same time. The practical way to build one is to compress stored energy in time.

Charge a capacitor slowly, then release it in a few hundred nanoseconds through the ignition transformer. A semiconductor switch struggles with that duty, because fast current risetimes force either very large devices or damaging snubber losses.

Magnetic pulse compression uses a chain of saturable inductors. Each one is passive, robust and lossless until the moment its core saturates, when it switches from high impedance to low impedance and transfers the energy downstream.

This article gives the core physics, the compression arithmetic worked through a three-stage chain, four pain points, six implementation steps, and the capacitor properties that make the stage time constants predictable.

2. Kernmechanismus

2.1 The charge interval

A compression stage holds a storage capacitor, a saturable inductor and the next stage's capacitor. During the charge interval the core sits unsaturated and presents a large inductance.

t_charge = π √(L_unsat C_n)

where t_charge is the charge interval in seconds, L_unsat is the unsaturated inductance of the saturable inductor, and C_n is the storage capacitance of stage n. A 100 µs charge interval into a 4.7 nF capacitor needs 216 mH of unsaturated inductance.

2.2 The compression ratio

When the capacitor voltage reaches its design value the core saturates, the inductance collapses, and the energy transfers into the next capacitor in a fraction of the charge time.

CR = t_charge / t_discharge = √(L_unsat / L_sat)

where CR is the compression ratio of the stage, t_discharge is the transfer interval, and L_sat is the saturated inductance. The ratio follows directly from the inductance swing, so a core that saturates to 1 % of its unsaturated value gives CR = 10, one that saturates to 3 % gives CR = 5.8, and a ratio of 15 requires the inductance to fall to 0.44 %.

2.3 Core sizing from the volt-second product

The core cross-section comes from Faraday's law integrated over the charge interval.

∫ V(t) dt = N A_core ΔB_sat

where the integral is the volt-second product of the charging waveform, N is the number of turns, A_core is the core cross-sectional area, and ΔB_sat is the usable flux swing. A 10 kV stage charged over 100 µs presents 1 V·s, so the core area and the turns count come from the capacitance and the charge time, and no steady-state current rating enters the calculation.

2.4 The chain and the impedance ladder

A chain of m stages multiplies the individual ratios, and the capacitance falls by one factor of CR at every step.

t_final = t_initial / (CR₁ CR₂ … CR_m)

where t_final is the output pulse width, t_initial is the charge interval of the first stage, and CR₁ through CR_m are the stage ratios. Three stages at CR = 10 turn a 100 µs charge into a 100 ns discharge.

Holding the energy constant across the chain sets the rest of the ladder. The capacitance falls by 10 per stage, so the voltage rises by √10, and the peak current rises by √10, while the characteristic impedance stays fixed because the saturated inductance falls in step with the capacitance.

E = ½ C V²

where E is the stored energy, C is the stage capacitance, and V is the stage voltage. The 235 mJ stored in stage 1 at 10 kV appears unchanged at 47 pF and 100 kV in stage 3, where the saturated inductance is 21.6 µH and the characteristic impedance is still 678 Ω. The stage current rises from 14.7 A to 147 A across the chain.

Fig. 1 — Three compression stages at CR = 10 turn a 100 µs charge into a 100 ns discharge while the 235 mJ of stored energy stays constant.

3. Schwachstellen im Engineering

Pain Point 1: Core reset and remnant flux

After each pulse the core must return to a defined negative flux level, or the next pulse starts from an unknown point and the compression ratio drifts. A design without a reset winding, or one using a core material with low squareness, shows pulse-to-pulse jitter that appears as ignition timing scatter.

Pain Point 2: Capacitor ESL judged against the wrong inductance

The 8 nH of a screw-terminal capacitor looks significant against a saturated inductance of a few microhenries. In a first stage with 2.16 mH of saturated inductance it adds 0.0004 %, and even in the 21.6 µH final stage it adds 0.04 %. The interconnect, not the capacitor, is the term worth controlling, and the layout is where the compression ratio is actually lost.

Pain Point 3: Loss accumulation at high repetition rate

Core hysteresis, eddy currents and capacitor loss all scale with frequency and flux swing. Above a few hundred hertz the chain heats, the saturation flux density of the core falls with temperature, and the compression ratio degrades without any change to the circuit.

Pain Point 4: Voltage grading across the magnetic switch

Each stage sees a transient close to the full stage voltage. Uneven distribution across turns or across core layers starts partial discharge, and sustained discharge destroys the core insulation over time. The stage then stops compressing altogether, and the failure arrives with no visible external damage.

4. Entwurfsschritte

Strategy 1: Model the chain with the interconnect inductance included

Extract the ESL of every storage capacitor and the inductance of every connection, then check what the extra inductance does to the final stage. In a 21.6 µH stage a 500 nH connection adds 2.3 % to the saturated inductance and costs about 1 % of the compression ratio, so the allowance belongs to the wiring.

Strategy 2: Design the reset circuit explicitly

Use a reset winding with a controlled current, or a resistor-diode reset, to return the core flux to a fixed negative level before every event. Verify the reset current in the pre-fire sequence, and do not take the schematic's word for it.

Strategy 3: Match the core to the repetition rate

Choose nanocrystalline tape for low eddy loss, derate the saturation flux density by 10 % at the maximum module temperature, and characterize the B-H loop at the operating frequency and temperature before freezing the design.

Strategy 4: Grade the voltage and manage the insulation

Use segmented windings with equal voltage per layer, encapsulate the core assembly in void-free resin, and verify partial discharge at 120 % of the maximum stage voltage. Target the same 5 pC floor that the capacitors in the chain meet.

Strategy 5: Instrument the chain

Fit a fast voltage probe at each stage capacitor and a Rogowski coil at the final stage, and log the compression ratio per ignition event. Alarm when the ratio drops below 80 % of nominal, which is the earliest symptom of core or capacitor aging.

Strategy 6: Pair the chain with low-ESL storage capacitors

Verlegen Sie N4700 (T3M) Class I parts: a SrTiO3 dielectric with tanδ at or below 0.1 %, a temperature coefficient of ±30 ppm/°C, 1 kV to 100 kV ratings and PD below 5 pC. A compact body keeps both ESR and ESL low, and a Folienkondensator with a higher loss factor and a larger loop works against the final stage.

Komponentenparameter	Typischer Wert	Testbedingung
Nennspannung (HVCT8G-Serie)	10 kV DC	Hi-Pot 1.5× für 60 s
Kapazität	4700 pF ±20% (472M)	1 MHz, 1 V<sub>eff</sub>
ESR bei 1 MHz	unter 50 mΩ	25 ° C
Schleifeninduktivität (E40-Sehne)	unter 8 nH	40 mm Anschlussabstand
Isolationswiderstand	über 10 GΩ bei 500 V Gleichstrom	25 °C, 60 % relative Luftfeuchtigkeit
Temperaturbereich	−40 °C bis +125 °C	IEC 60068-2-Reihe
Impuls-dv/dt-Fähigkeit	über 50 kV/µs	bei Nennspannung

5. HVC capacitors for compression chains

Three properties keep a stage time constant predictable: low ESR, low ESL and a stable capacitance across temperature and pulse count. HVC builds N4700 parts for all three.

Sechs Parameter, die hier von Bedeutung sind

• tanδ at or below 0.1 % keeps the stage loss small, so the chain does not heat its own cores and shift the compression ratio.
• ±30 ppm/°C holds the stage capacitance, and therefore the charge interval, steady from the first pulse of a shift to the last.
• PD below 5 pC keeps the storage capacitors from becoming discharge sources inside a sealed, voltage-stressed chain.
• 1 kV to 100 kV ratings match the per-stage voltage of compact pilot igniters through multi-stage main-arc injectors.
• Das HVCT8G screw-terminal cylindrical package carries the final stage's peak current without lead cracking or dielectric fatigue.
• Field record: an HVC 40 kV / 441 screw-type capacitor replaced international first-tier parts in high-voltage field-service programs, and the same construction matches the electrical parameters of Querverweis Kandidaten.

Lieferung und Support

Standardbauteile werden innerhalb von 4–8 Wochen, aufeinander abgestimmte Anlagen innerhalb von 6–10 Wochen geliefert. Oberhalb von 1 kV ist die Anlage als Reihenschaltung mit passenden Komponenten verfügbar. Bemessung von Widerständen for the stage divider.

Send the required final pulse width, peak current, tank voltage and repetition rate. HVC returns a stage-by-stage capacitor recommendation with ESL and ESR data plus core sizing guidance for the inductance ladder.

6. Häufig gestellte Fragen

Q1: How is the compression ratio of one stage defined?

As the square root of the inductance swing. CR = √(L_unsat/L_sat), so a core that saturates to 1 % of its unsaturated inductance gives CR = 10, and 3 % gives CR = 5.8.

Q2: How large is a three-stage compression chain?

It depends on the pulse width, not on the energy. Three stages at CR = 10 take a 100 µs charge to 100 ns, with stage capacitances of 4.7 nF, 470 pF and 47 pF at 10 kV, 31.6 kV and 100 kV.

Q3: Does the capacitor ESL limit the compression?

Barely. Eight nanohenries against the 21.6 µH of a final stage adds 0.04 %. The wiring between stages carries hundreds of nanohenries and is the term worth controlling.

Q4: What sets the core cross-section?

The volt-second product. ∫V dt must equal N A_core ΔB_sat over the charge interval, so a 10 kV stage charged for 100 µs presents 1 V·s and the core area follows from that.

Q5: Why does the compression ratio drift at high repetition rate?

Core loss heats the tape, and saturation flux density falls with temperature. Derate ΔB_sat by 10 % at the maximum module temperature and characterize the B-H loop at the real operating frequency.

Q6: How do I know the chain is aging?

Log the compression ratio per event with a fast probe on each stage capacitor and a Rogowski coil at the output. A ratio below 80 % of nominal is the earliest sign of core or capacitor degradation.

7. Referenzen

1. E. Kuffel, W. S. Zaengl, J. Kuffel, Grundlagen der Hochspannungstechnik, 2. Aufl., Newnes, 2000.
2. N. Mohan, TM Undeland, WP Robbins, Leistungselektronik: Wandler, Anwendungen und Design, 3. Auflage, Wiley, 2003.
3. MIL-HDBK-217F Mitteilung 2, Zuverlässigkeitsvorhersage elektronischer Geräte 1995.
4. IEC 60384-1:2021, Festkondensatoren für den Einsatz in elektronischen Geräten – Teil 1: Allgemeine Spezifikation, 6. Aufl. Genf: IEC, 2021.
5. IEC 61071:2017, Kondensatoren für Leistungselektronik, 2. Aufl. Genf: IEC, 2017.
6. ГОСТ IEC 61071-2014, Elektrische Silokondensatoren (Kondensatoren für die Leistungselektronik). Moskau: Standardformat, 2014.
7. H. Liu et al., Einfluss elektromagnetischer Felder auf das Teilentladungsverhalten in BOPP-FolienkondensatorenIEEE Transactions on Dielectrics and Electrical Insulation, Bd. 30, Nr. 6, S. 2617–2624, 2023. https://doi.org/10.1109/tdei.2023.3304600
8. P. Morshuis und M. Jeroense, Raumladung in der Isolierung von HGÜ-Kabeln, in: IEEE 1997 Annual Report Conference on Electrical Insulation and Dielectric Phenomena, S. 28-31, 1997. https://doi.org/10.1109/ceidp.1997.634551.
9. AN2001_06 — Reihenschaltung von IGBTs, Infineon Technologies, AN2001_06, http://www.infineon.com/dgdl/Infineon-AN2001_06_Series_connection_of_IGBTs-AN-v1.0-en.pdf?fileId=db3a304412b407950112b40f000d12f7 .
10. US 4,521,889, Microstrip Capacitor for Energy Storage, Kraftwerk Union AG, 1985, https://www.osti.gov/biblio/6349373 .
11. HVC-Anwendungsentwicklungsteam Hochspannungs-Keramikkondensator Technische Ressourcen, https://www.hv-caps.com